1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, particularly to an art effectively applied to a semiconductor integrated circuit having a multilayer wiring structure.
2. Description of the Related Art
In the case of a semiconductor integrated circuit, a product is born which has a multilayer wiring structure constituted by forming a large-scale circuit device group on the surface of a semiconductor substrate and alternately heaping an insulating layer and a wiring layer to be electrically connected. Some of the semiconductor integrated circuits have a memory in which important confidential information is included or a circuit including an advanced intellectual property. Therefore, it may be preferable to take action so that information is not altered or analyzed.
Moreover, there is a problem that electromagnetic noises are radiated to the outside of a semiconductor integrated circuit to cause another semiconductor integrated circuit to malfunction depending on the amplitude of a clock signal or the like in the semiconductor integrated circuit and a hazard that the semiconductor integrated circuit malfunctions due to electromagnetic noises from another unit. Conventionally, to prevent the problems, the technique disclosed in Japanese Unexamined Publication No. 74771/1993 (prior art) has been used so far. In the case of the structure disclosed in the prior art, as shown in FIGS. 18 and 19, a multilayer wiring structure is used and a shielding film 1 is formed so as to cover almost the entire surface of a semiconductor integrated circuit by avoiding a terminal 2a for inputting or outputting signals.
However, as described above, by forming the shielding film 1 on almost the entire surface of the semiconductor chip, a problem occurs that a stress caused by a difference between thermal expansion coefficients of the shielding film 1 and an interlayer insulating film 7 or a difference between thermal expansion coefficients of the shielding film 1 and a semiconductor substrate 4 increases and a shift between the shielding film 1 and interlayer insulating film 7 increases or a warpage increases when the semiconductor chip is thin.
For example, in the case of an aluminum film used as a shielding film and a silicon nitride film used as an interlayer insulating film, the aluminum film used as the shielding film has a larger thermal expansion coefficient. Therefore, when passing through a heat treating step of a semiconductor fabrication process, the shielding film is more expanded than the interlayer insulating film. It is preferred that the expansion can be absorbed with the aluminum film. However, because the aluminum film covers almost the entire surface, thermal expansion cannot be absorbed, a convex warpage occurs which is formed when the central portion of a wafer protrudes, a shift occurs between the shielding film and interlayer insulating film, and resultantly a device malfunctions.
Moreover, there are some thin semiconductor devices of an IC card or the like, in which the thickness of a semiconductor chip to be mounted is less than 200 μm. In this case, for example, the thermal expansion coefficient of an aluminum film serving as a shielding film is larger than that of the single-crystalline silicon of a semiconductor substrate and therefore, a warpage occurs more remarkably.
Furthermore, when forming a plane not parallel with the surface of a semiconductor substrate on the back of the substrate as a countermeasure to prevent analysis by applying infrared radiation from the backside of the semiconductor substrate, a warpage occurs in which the central portion of the surface of the semiconductor substrate becomes convex. When covering the entire surface of the semiconductor substrate with a shielding film, the warpage becomes more remarkable. Therefore, it is difficult to use the shielding film for the entire surface.